Semiconductor devices are used in a variety of electronic applications, such as computers, cellular phones, personal computing devices, and many other applications. Home, industrial, and automotive devices that in the past comprised only mechanical components now have electronic parts that require semiconductor devices, for example.
Semiconductor devices typically include several layers of insulating, conductive and semiconductive materials that are patterned to form integrated circuits. There may be a plurality of transistors, memory devices, switches, conductive lines, diodes, capacitors, logic circuits, and other electronic components formed on a single die or chip. Semiconductor technology has seen a trend towards miniaturization, to meet the demands of product size reduction, improved device performance, and reduced power requirements in the end applications that semiconductors are used in, for example.
The manufacturing process for semiconductor devices is typically referred to in two phases: the front-end-of-line (FEOL) and the back-end-of-line (BEOL). The FEOL is typically defined as the processing steps that begin with a starting semiconductor wafer or workpiece up to the formation of the first metallization layer, and the BEOL is defined as the processing steps from that point forward, for example.
In the past, integrated circuits contained a relatively small number of devices per chip or die, and the devices could be easily interconnected. However, in more recent integrated circuit designs, there may be hundreds or thousands of devices on a single chip, resulting in the need for multilevel interconnect systems, wherein the area for interconnect lines is shared among two or more material levels.
As the minimum line width on integrated circuits becomes smaller, the active device density increases, and the time required for transistors to charge capacitive loads becomes limiting on the performance of the integrated circuit. Also, as the chip size increases, the interconnect path lengths also increase. Thus, many large ultra-large scale integration (ULSI) circuits are limited by interconnect propagation delay time. The propagation delay of integrated circuits becomes limited by the RC delay of the interconnection lines when the minimum feature size decreases below about 1 μm, for example, which limits the circuit speeds. The RC delay refers to the resistance (R) of the conductive lines used for the interconnect lines and the capacitance (C) between the conductive lines.
One challenge in the semiconductor industry is to reduce and minimize the RC delay of integrated circuits, in order to improve device performance and increase device speed. The resistive or R component of RC delay is being addressed by a move from the use of aluminum to copper, which has a lower resistance than aluminum, as the material for conductive lines. The C or capacitive component of RC delay is being addressed by the use of insulating materials between the conductive lines that comprise a lower dielectric constant (k) than materials such as SiO2 that were used in the past for inter-metal dielectric (IMD). However, most low k insulating materials are structurally weak.
Another challenge in fabricating semiconductor devices is that electrical contact must be made from the very small chip or integrated circuit to leads of a package, or to other chips, in a multi-chip module, for example. The electrical contact to an integrated circuit is made using wire bonds that are wire bonded to bond pads on the chips. The wire bonding process involves placing a wire, typically comprising gold or other metal, against a bond pad on the integrated circuit, and applying pressure to the wire while vibrating the wire, causing the wire to become bonded to the bond pad. Destructive wire bond strength tests (e.g., the test chips are discarded after the tests) are typically performed on a small number of semiconductor devices in a lot after the wire bonding process, in which an upward force is applied to a wire to determine how much force it takes to lift the wire from the bond pad.
If the material layers beneath the bond pad are weak, the semiconductor device may be damaged during the wire bonding process. Furthermore, when tests on the wire bonds are performed, damage and lift-off of the bond pads can occur. For example, portions of the material layers beneath and adjacent the bond pad may be pulled away or lifted during the wire bond strength tests. The introduction of low k materials as insulating materials in semiconductor device manufacturing has made pad stacks for wire bonding more critical because of the weaker material properties of the low k materials.
Therefore, some recent semiconductor designs have support structures formed in the metallization layers beneath the bond pads in the low k insulating material layers. However, some of these prior art support structures take up valuable real estate on chips. For example, the presence of support structures in the bond pad region prohibits or limits the use of the area under the bond pads from being used as functional conductive lines, e.g., for the electrical wiring of the semiconductor device, in the low k insulating material layers.
Furthermore, prior art support structures are formed only in conductive line and via layers having a low k material, e.g., comprising a dielectric constant of less than the dielectric constant of SiO2, or having a k value of less than about 3.9. Forming support structures in only the low k material layers causes stress fractures, delamination of the low k material due to sheer force stress, and an increased risk of tear-outs during wire bond tests, for example.
Thus, what are needed in the art are improved support structures for providing mechanical support for wire bond areas of semiconductor devices, particularly in semiconductor devices having low k insulating materials as dielectric layers.